library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity FORMATO is
    port(
         clk: in std_logic;
			enable: in std_logic;
	 		Input: in std_logic_vector(14 downto 0);
	 		Output: out std_logic_vector(14 downto 0)
   	);
end FORMATO;



architecture arch of FORMATO is
begin
    process(clk)
    begin
      if rising_edge(clk) then
			if enable='0' then
            Output <= Input;
			end if;
		end if;
	end process;
end arch; 
